Current Limited Voltage Supply

ABSTRACT

A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit.

FIELD OF THE INVENTION

The present invention relates to integrated circuits using standard CMOStechnology. More specifically, the present invention relates to anintegrated circuit having a current limited voltage supply.

RELATED ART

In conventional semiconductor integrated circuit devices, standarddigital logic cells are designed to have an output driving capabilitysufficient to drive an output signal at a selected frequency underworst-case load conditions. As a result, relatively high switchingcurrents will flow through the standard digital logic cells duringnormal operating conditions, thereby leading to high power consumption.The high switching currents flowing through the standard digital logiccells may also cause noise to be introduced to the power supply lines ofthe integrated circuit device, thereby adversely affecting operation ofthe integrated circuit device. To help alleviate these problems,variable current sources have been coupled to standard digital logiccells in order to limit the switching currents.

FIG. 1A is a circuit diagram of a conventional semiconductor integratedcircuit device 100 that includes a standard digital logic cell 2 astructured as a CMOS inverter, a standard digital logic cell 2 bstructured as a NAND gate, and a standard digital logic cell 2 cstructured as a NOR gate. Each of these standard digital logic cells 2a-2 c is coupled to a corresponding variable current source 10 a-10 c.Each of the variable current sources 10 a-10 c includes a correspondingNMOS transistor 13 a-13 c, wherein the drains of these transistors 13a-13 c are connected to the corresponding standard digital logic cells 2a-2 c. The sources of NMOS transistors 13 a-13 c are connected toground, and the gates of NMOS transistors 13 a-13 c are commonlyconnected to bias line 12. The bias line 12 receives a bias voltageV_(B) from a bias voltage generating circuit, which includes a constantcurrent source 14 and an NMOS transistor 15. The drain and gate of NMOStransistor 15 are connected to the bias line 12, and the source of NMOStransistor is connected to ground. The constant current source 14 causesa constant bias current I_(B) to flow through NMOS transistor 15, suchthat the bias voltage V_(B) is equal to the gate-to-source voltageV_(GS) of NMOS transistor 15. This bias voltage V_(B) is applied to thegates of NMOS transistors 13 a-13 c, thereby limiting the currentflowing from each of the standard digital logic cells 2 a-2 c to ground.The bias voltage V_(B) is set to a value that attempts to limit powerconsumption and noise within standard digital logic cells 2 a-2 c.

In order to achieve lower DC current consumption within device 100 (asmay be required by certain applications), the variable current sources10 a-10 c must increasingly limit the current flow from the standardcells 2 a-2 c to ground. However, if the current flowing from each ofthe standard digital logic cells 2 a-2 c to ground is limited too much,then the circuitry present within the standard digital logic cells 2 a-2c may not operate correctly (i.e., may not be capable of switching atthe desired frequency). Thus, the effectiveness of variable currentsources 10 a-10 c is limited. Semiconductor integrated circuit device100 is described in more detail in U.S. Pat. No. 5,225,720 to Kondoh etal. (hereinafter, the Kondoh '720 Patent).

Note that the Kondoh '720 Patent describes alternate embodiments for thevariable current source 10 a, which are briefly described below.

FIG. 1B is a circuit diagram which illustrates one alternate embodimentdescribed by the Kondoh '720 Patent. In this alternate embodiment, avariable current source is provided at the Vdd power supply side of eachstandard digital logic cell (rather than at the ground side of eachstandard digital logic cell). For example, a variable current source 10a′, which comprises PMOS transistor 41, is interposed between the Vddpower supply 7 and the standard digital logic cell 2 a. The gate of PMOStransistor 41 is connected to receive a bias voltage V_(B), which isprovided by bias voltage generating circuit 50. Bias voltage generatingcircuit 50 includes PMOS transistor 51 and constant current source 14.The bias voltage V_(B) limits the current flowing from the Vdd supplyvoltage 7 to the standard digital logic cell 2 a. Again, the biasvoltage V_(B) is set to a value that attempts to limit power consumptionand noise within the standard digital logic cell 2 a. However, thecircuit of FIG. 1B exhibits the same deficiencies as the circuit of FIG.1A.

FIG. 1C is a circuit diagram which illustrates another embodimentdescribed by the Kondoh '720 Patent. In this alternate embodiment, avariable current source is provided at both the Vdd power supply sideand the ground side of each standard digital logic cell. For example,the variable current sources 10 a and 10 a′ are both coupled to thestandard digital logic cell 2 a. The gate of PMOS transistor 41 isbiased by a first bias voltage V_(B1) provided on bias line 12′, and thegate of NMOS transistor 13 is biased by a second bias voltage V_(B2)provided on bias line 12. The bias voltages V_(B1) and V_(B2) areprovided by bias voltage generating circuit 60, which includes constantcurrent source 14, NMOS transistors 15 and 61 and PMOS transistor 51.The bias voltages V_(B1) and V_(B2) limit the current flowing throughthe standard digital logic cell 2 a. Again, the bias voltages V_(B1) andV_(B2) are set to values that limit the power consumption and noisewithin the standard digital logic cell 2 a. However, the circuit of FIG.1C exhibits the same deficiencies as the circuit of FIG. 1A.

It would therefore be desirable to have a method and structure forlimiting power consumption and noise within a standard digital logiccell, without preventing the proper operation of the standard digitallogic cell.

SUMMARY

Accordingly, the present invention provides a current limited voltagesupply, which includes a transistor and a capacitor, for poweringdigital logic cells of an integrated circuit. The transistor isconnected in a current mirror configuration with a bias circuit, suchthat a constant reference current is mirrored through the transistor toprovide a limited supply current. The transistor is coupled to thedigital logic cells and the capacitor. The limited supply current isused to charge the capacitor while the digital logic cells are notswitching. However, while the digital logic cells are switching, thecapacitor discharges to the digital logic cells, thereby providing thedigital logic cells with sufficient energy to implement high-speedswitching. The capacitor also minimizes voltage fluctuations within inthe current limited voltage supply, such that analog circuitry can bereliably powered from a different branch of the same current mirrorcircuit.

The present invention will be more fully understood in view of thefollowing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B and 1C are circuit diagrams of conventional semiconductorintegrated circuit devices having variable current sources coupled tostandard digital logic cells.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit chipthat includes a current limited voltage supply in accordance with oneembodiment of the present invention.

DETAILED DESCRIPTION

FIG. 2 is a circuit diagram of a semiconductor integrated circuit (IC)chip 200 in accordance with one embodiment of the present invention. ICchip 200 includes a current limited voltage supply 210, a bias circuit220, analog circuit 230, digital cell supply line 240 and standarddigital logic cells 250 ₁-250 _(N). Digital logic cells 250 ₁-250 _(N)may include, for example, inverters and/or logic gates, which haveoutput signals that switch between logic states in response to one ormore input signals. Each of the digital logic cells 250 ₁-250 _(N) iscoupled between the digital cell supply line 240 and ground. Asdescribed in more detail below, the digital supply line 240 receives asupply current I_(D) from the current limited voltage supply 210. Avoltage V_(D) is developed on the digital supply line 240.

In accordance with one embodiment, current limited voltage supply 210includes a P-channel MOS transistor 211 and an integrated capacitor 212.The source of P-channel MOS transistor 211 is coupled to the V_(DD)(positive) voltage supply rail, the drain of P-channel MOS transistor211 is coupled to the digital supply line 240, and the gate of P-channelMOS transistor 211 is coupled to receive a bias voltage V_(BIAS) frombias circuit 220. Capacitor 212 includes an electrode connected to thedrain of P-channel MOS transistor 211 (and the digital supply line 240),and a counter-electrode connected to ground.

In the described embodiment, bias circuit 220 includes P-channel MOStransistors 221-222, N-channel MOS transistors 223-224 and constantcurrent source 225. Constant current source 225 causes a referencecurrent I_(REF) to flow through N-channel MOS transistor 224. N-channelMOS transistors 223 and 224 are connected in a current mirrorconfiguration, such that the reference current I_(REF) is mirrored toN-channel MOS transistor 223 as the reference current I_(REF1). Notethat the relationship between the reference currents I_(REF) andI_(REF1) is determined by the relative sizes of N-channel MOStransistors 223 and 224, in a manner understood by those of ordinaryskill in the art. For example, if the N-channel MOS transistors 223 and224 are identical, then the reference currents I_(REF) and I_(REF1) willbe equal.

The reference current I_(REF1) also flows through P-channel MOStransistor 221, which is connected in series with N-channel MOStransistor 223. P-channel MOS transistor 221 is connected in a currentmirror configuration with the P-channel MOS transistor 211 of currentlimited voltage supply 210, such that the reference current I_(REF1) ismirrored to P-channel MOS transistor 211 as the source current I_(S).Again, the relationship between the reference current I_(REF1) and thesource current I_(S) is determined by the relative sizes of P-channelMOS transistors 221 and 211. Note that the bias voltage V_(BIAS)developed on the gate of P-channel MOS transistor 211 is equal to theV_(DD) supply voltage minus the gate-to-source voltage V_(GS) ofP-channel MOS transistor 221.

P-channel MOS transistor 221 is also connected in a current mirrorconfiguration with the P-channel MOS transistor 222, such that thereference current I_(REF1) is mirrored to P-channel MOS transistor 222as the analog supply current I_(A). Again, the relationship between thereference current I_(REF1) and the analog supply current I_(A) isdetermined by the relative sizes of P-channel MOS transistors 221 and222. The DC analog supply current I_(A) is provided to analog circuitry230 on the same IC chip 200. Analog circuitry 230 may include, forexample, current and voltage references, amplifiers, comparators,oscillators, active filters, analog-to-digital converters, digital toanalog converters, and other circuits apparent to those of ordinaryskill in the art.

Returning now to current limited voltage supply 210, bias circuit 220limits the digital cell source current I_(S) to a predetermined value,which is selected in view of the characteristics of digital logic cells250 ₁-250 _(N). More specifically, the digital cell source current I_(S)is selected to minimize the DC current consumption within digital logiccells 250 ₁-250 _(N), while allowing for proper operation of thesedigital logic cells. The voltage (V_(D)) developed on the drain ofP-channel MOS transistor 211 charges capacitor 212, thereby causingcapacitor 212 to store energy that will subsequently be supplied todigital logic cells 250 ₁-250 _(N). In the described embodiment, thevoltage developed on the drain of P-channel MOS transistor 211 isapproximately equal to the V_(DD) supply voltage.

Logic transitions in the digital logic cells 250 ₁-250 _(N) will tend tointroduce current spikes in the supply current I_(S). Such currentspikes, left unmitigated, may introduce noise in the current mirrorcircuitry present in bias circuit 220. Such noise may adversely affectthe operation of analog circuit 230.

In accordance with one embodiment of the present invention, capacitor212 reduces spikes in the supply current I_(S), which could otherwiseresult from switching (i.e., logic transitions) within digital logiccells 250 ₁-250 _(N). More specifically, capacitor 212 stores energy(i.e., a charging current I_(C) flows into capacitor 212, therebycharging this capacitor) in the intervals between logic transitions indigital logic cells 250 ₁-250 _(N). During logic transitions in thedigital logic cells 250 ₁-250 _(N), capacitor 212 discharges (i.e., adischarging current I_(C) flows out of capacitor 212 to digital supplyline 240), thereby providing the energy necessary for the digital logiccells 250 ₁-250 _(N) to switch rapidly, and reducing spiking of thesupply current I_(S). In this manner, capacitor 212 compensates for lowDC current within digital logic cells 250 ₁-250 _(N) during fast logictransitions, thereby assuring that digital logic cells 250 ₁-250 _(N)operate with a fast transient time and low average power consumption.

Note that by reducing the spiking of the supply current I_(S), capacitor212 also reduces voltage fluctuation on supply line 240 during logictransitions within digital logic cells 250 ₁-250 _(N).

In accordance with one embodiment, the size of capacitor 212 is selectedin view of the current I_(S) supplied by P-channel MOS transistor 211and the width-to-length (W/L) ratios of the transistors in digital logiccells 250 ₁-250 _(N), as these parameters will define the currentspiking characteristics of the supply current I_(S). For example, duringnormal operation of digital logic cells, the switching of digital logiccells 250 ₁-250 _(N) may result in a current (I_(D)) increase of 100microAmps during a period of 20 nanoseconds. In this case, capacitor 212discharges to supply this current. The size of capacitor 212 willdetermine the voltage fluctuation of supply line 240 under theseconditions. For example, to limit the voltage fluctuation to 100milliVolts, capacitor 212 should have a capacitance of 20 pico-Farads.Note that this determination is made using the equation CV=Q, wherein Cis the capacitance of capacitor 212 (in Farads), V is the voltagefluctuation on supply line 240 (in Volts), and Q is the required chargesupplied by capacitor 212 during the switching transistion of digitallogic cells 250 ₁-250 _(N) (in coloumbs). Note that the required chargeQ is equal to current increase caused by the switching of digital logiccells 250 ₁-250 _(N) (in Amps) multiplied by time (in seconds).

Although the invention has been described in connection with severalembodiments, it is understood that this invention is not limited to theembodiments disclosed, but is capable of various modifications, whichwould be apparent to one of ordinary skill in the art. Accordingly, thepresent invention is only limited by the following claims.

1. An integrated circuit comprising: a plurality of digital logic cells that undergo logic transitions during normal operation of the integrated circuit; a supply line coupled to the digital logic cells, wherein the supply line provides a supply current to the digital logic cells during normal operation of the integrated circuit; a current limited voltage supply comprising a transistor coupled between a first voltage supply terminal and the supply line, and a capacitor coupled to the supply line, wherein the capacitor supplies a discharging current to the supply line while the digital logic cells undergo logic transitions.
 2. The integrated circuit of claim 1, wherein the capacitor receives a charging current from the transistor during periods while the digital logic cells do not undergo logic transitions.
 3. The integrated circuit of claim 1, wherein the transistor is a P-channel MOS transistor, and the first voltage supply terminal provides a positive supply voltage.
 4. The integrated circuit of claim 1, wherein the capacitor is further coupled to a second voltage supply terminal.
 5. The integrated circuit of claim 4, wherein the second voltage supply terminal is a ground supply terminal.
 6. The integrated circuit of claim 1, further comprising a bias circuit coupled to the transistor of the current limited voltage supply, wherein the bias circuit applies a bias voltage to the transistor to limit a first current through the transistor.
 7. The integrated circuit of claim 6, wherein the bias circuit comprises a current mirror circuit that translates a reference current to the transistor.
 8. The integrated circuit of claim 7 further comprising an analog circuit, wherein the bias circuit further comprises a current mirror circuit that translates the reference current to the analog circuit.
 9. An integrated circuit comprising: a current mirror circuit that translates a reference current into a first supply current through a first transistor; a plurality of digital logic cells coupled between a drain of the first transistor and a ground supply terminal; and a capacitor coupled between the drain of the first transistor and the ground supply terminal.
 10. The integrated circuit of claim 9, wherein the digital logic cells undergo logic transitions during normal operation of the integrated circuit, wherein the capacitor is charged from the first supply current when the digital logic cells are not undergoing logic transitions, and wherein the capacitor is discharged through the digital logic cells while the digital logic cells are undergoing logic transitions.
 11. The integrated circuit of claim 9, further comprising an analog circuit, wherein the current mirror circuit further translates the reference current into a second supply current through a second transistor, wherein the second supply current is provided to the analog circuit.
 12. A method of operating an integrated circuit comprising: generating a first supply current by mirroring a constant reference current through a first transistor; powering digital logic cells of the integrated circuit from the first supply current, wherein the digital logic cells undergo logic transitions during normal operation of the integrated circuit; charging a capacitor from the first supply current during a first period, wherein the digital logic cells are not undergoing logic transitions during the first period; and discharging the capacitor to the digital logic cells during a second period, wherein the digital logic cells are undergoing logic transitions during the second period.
 13. The method of claim 12, further comprising: generating a second supply current by mirroring the constant reference current through a second transistor; and powering analog circuitry of the integrated circuit from the second supply current. 